1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods of forming halo regions.
2. Description of the Related Art
A typical field effect transistor implemented on a semiconductor substrate consists of a gate dielectric layer-gate electrode stack positioned on the substrate, and opposing source/drain impurity regions positioned in the substrate below the stack. The lateral separation between the pn junctions of the source/drain regions generally defines the channel length of the transistor. Some source/drain regions include extension regions that project laterally into the channel beneath the gate. When lightly doped, these extension structures are sometime called lightly doped drains (“LDD”). The purpose of the LDD structures is to provide a region of lighter doping beneath the gate electrode to reduce the drain junction potential.
Scaling of field effect transistor devices has historically been, and continues to be a fundamental goal in the semiconductor fabrication industry. The continual drive toward higher circuit density has been fueled by demands from ordinary consumers, industry, government and the military for ever increasing speed, capability and miniaturization of electronic products, as well as the desire of semiconductor manufacturers to reduce manufacturing costs. Scaling efforts have thus far been highly successful. Two micron processing, considered state of the art a little more than a decade ago, has given way to sub-micron processing.
As in many aspects of semiconductor processing, current efforts to scale transistor geometry involve a set of trade-offs between higher packing density, improved device performance, and short channel effects. As process technologies scaled below about 2.0 μm, a series of design difficulties arose stemming from the semiconductor physics associated with short-channel devices. Hot carrier effects and punchthrough become much more problematic in short channel devices, such as modern field effect transistors in sub-2.0 μm processing. Without compensatory processing techniques, short channel effects can either reduce device performance or lead to device failure or both.
Halo structures have been used for several years in n-channel, p-channel and CMOS technologies as a means of controlling short channel effects in sub-0.5 μm critical dimension processing. A conventional halo structure consists of an implanted impurity region positioned lateral to the LDD of each source/drain region and provided with the same conductivity type as the channel. The conventional method of fabricating a halo structure entails a single large-angle-tilted (“LAT”) ion implant that positions the halo structure around and under the vertical junctions of both the LDD and the overlapping heavier doped portion of the source/drain region. Halo regions are formed on both the source side and the drain side of the channel.
A difficulty associated with conventionally produced halo structures is the potential for limitations on carrier mobility and drive current to exist for a given level of leakage current. Halo regions positioned proximate both the source side and the drain side present an impediment to carrier mobility. The ability to reduce barriers to carrier mobility without significant increases in leakage currents holds the promise of squeezing even more performance out of halo implanted transistors.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.